-- Flip-Flop T

library ieee;
use ieee.std_logic_1164.all;

entity FF_T is 
	port ( 
			CLK, CLR, PRESET: in std_logic;
			T : in std_logic;
			QT: out std_logic
	);
end FF_T;

architecture DT_FLOW of FF_T is
signal Q_OUT : std_logic;
signal ENTRADA : std_logic;
begin
	ENTRADA <= T;
	process (CLK, CLR, PRESET)
	begin
		if (CLR = '0') then
			Q_OUT <= '0';
		elsif (PRESET = '1') then
			Q_OUT <= '1';
		elsif ((CLK'event) and (CLK = '0')) then
			case (ENTRADA) is
				when '0' =>
					Q_OUT <= Q_OUT;
				when '1' =>
					Q_OUT <= not(Q_OUT);
			end case;
		end if;
	end process;
	
	QT <= Q_OUT;
	
end DT_FLOW;